Signs 0.6.2 reviewDownload
Signs is a tool for logic synthesis and gate level simulation
Signs is a tool for logic synthesis and gate level simulation. Signs's project main features include synthesis of RTL-style VHDL circuit descriptions and a dynamic graphical netlist viewer.
Supported formats include VHDL, ISCAS, and limited support for BLIF, Verilog, and EDIF netlists. Various true value and fault simulators and a combinational ATPG are included for circuit testing.
Here are some key features of "Signs":
Written in Java, therefore platform-independent
Aims to be VHDL93 compliant, at the moment a VHDL Subset is supported
(Limited) support for non-synthesizable VHDL code, useful for testbenches
Synthesis of RTL-style sequential VHDL process descriptions according to IEEE Std 1076.6
Dynamic graphical netlist viewer supporting annotations (signal/gate names, signal values provided by simulators, faults)
VHDL netlist output to file
Input and output of netlists in ISCAS benchmark format
Gate level true value simulators: event-based (any circuit), bit-parallel (combinational circuits only)
Fault simulators: PPSFP, simple single faultsim
Input and output of pattern lists in WGL format
ATPG for combinational circuits: Implication-Graph based, PODEM
Limited support for Verilog and EDIF netlists
Pure command-line mode available besides GUI mode
Integrated environment including source code and netlist structure tree views, build system, compilers and editors with syntax highlighting
What's New in This Release:
Besides many bugfixes, this release features an improved Eclipse plugin that includes a new Signs console, autobuilder improvements, and outline view navigation.
The VHDL compiler has support for attribute elaboration and VHDL87 style file declarations, and reports precise source locations for netlist annotations and error messages.
New features in this release include an experimental Berkeley SIS interface, BLIF netlist output, adder and comparator generation, and better support for test benches.
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