Covered 0.4.8 reviewDownload
Covered is a Verilog code coverage analysis tool
Covered is a Verilog code coverage analysis tool. Covered can be useful for determining how well a diagnostic test suite is covering the design under test.
Typically in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document.
When the test suite contains all of the tests required by the design specification, the test writer may be asking him/herself, "How much logic in the design is actually being exercised?", "Does my test suite cover all of the logic under test?", and "Am I done writing tests for the logic?".
When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful.
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